Earlier this week, Texas Instruments announced two new SoCs (System-on-Chips) for the small-cell base-station market, adding an ARM A8 core while scaling down the architecture of the TCI6618, which they had announced for the high-end base-station market at MWC (Mobile World Congress).
|Cognitive radios will be enable spectrum re-use
in both the frequency and time domains. (source – Mindspeed)
While 4G networks are still just emerging, Johnston went on to boldly describe the attributes of future 5G networks – self-organizing architectures enabled by software-defined cognitive radios. Service providers don’t like the multiple frequency bands that make up today’s networks, he said, because there are too many frequencies dedicated to too many different things. As he described it, 5G will be based on spectrum sharing, a change from separate spectrum assignments with a variety of fixed radios, to software-defined selectable radios with selectable spectrum avoidance.
|Software-defined cognitive radios will enable dynamic spectrum sharing,
including the use of “white spaces” (source Mindspeed)
Touching on the topic of “white spaces“, Johnston said that the next step will involve moving to dynamic intelligent spectral avoidance, what he called “The Holy Grail”, with the ability to re-use spectrum across both frequency and time domains, and to dynamically avoid interference.
|Mindspeed’s Transcede 4000 contains 10 MAP cores, 10 CEVA x1641 DSP cores, and 6 ARM A9 cores, in a 40nm 800M transistor SoC (source Mindspeed)|
The Transcede 4000 contains 10 MAP (Mindspeed application processors) cores, 10 CEVA x1641 DSP cores, and the 6 ARM A9 cores – in dual and quad configurations. Designers can use the Transcede on-chip network to scale up to networks of multiple SoCs, in order to construct larger base-stations. How far apart you can place the SoCs depends on what type of I/O (input-output) transceivers you use. With optical fiber transceivers, the multicore processors can be kilometers apart (see Will 4G wireless networks move basestations to the cloud? ) to share resources for optimization across the network. The dual core ARM-A9 processor in the Transcede 4000 has an embedded real time dispatcher that assigns tasks to the chip’s 10 SPUs (signal processing units), which consist of the combination of a CEVA X1641 DSP and MAP core. To build a base-station with multiple Transcedes, designers can assign one device’s dual core as the master dispatcher to manage the other networked processors.
The evolution of software complexity is also a challenge, with complexity increasing 200X from the less than 10,000 lines of code in the days of dial-up modems, to 20M lines of code to perform 4G LTE baseband functions. Software engineers must support multiple legacy 2G and 3G standards in 4G eNodeB base-stations, in order to enable migration and multi-mode hardware re-use. Since the C-programming language does not directly support parallelism, Mindspeed takes the C-threads and decomposes them to fit within the multicore architecture, says Johnston.